Integration and Communications

The power of the Neural Decision Processor (NDP) is only realized when it is effectively integrated into a larger system. Section 5.2 explores the bridge between the high-efficiency silicon and the end-product. This involves moving from a "chip-level" perspective to a System-level perspective—focusing on how the intelligence is packaged, how it communicates with host controllers, and how it manages the power dynamics of the entire device.

A. The Hardware Hierarchy: From Silicon to System Integrating Edge AI requires balancing three distinct layers of hardware interaction:

1. Sensor Input: Managing the high-speed data flow from microphones (PDM/I2S) or motion sensors (SPI/I2C) directly into the NDP.

2. The Module (SOM): Utilizing the TML120 to simplify the physical implementation, ensuring stable power delivery and clocking.

3. Host Communication: Establishing a reliable command-and-control link between the NDP "Gatekeeper" and the primary Application Processor (AP).

B. The "Interrupt-Driven" Philosophy

The core principle of eFabric™ integration is the Wake-on-Pattern mechanism. In a traditional "Polling" architecture, the main CPU stays awake to constantly check sensor data, which is a massive energy drain.

• The Integration Strategy: The NDP is integrated as an autonomous peripheral. It processes the stream of data in complete isolation.

• The Trigger: Only when a neural network match exceeds a predefined confidence threshold does the NDP toggle a physical Interrupt Pin (IRQ). This signal acts as a "tap on the shoulder" to wake the host controller from its deep sleep.

C. Protocol Selection: SPI vs. UART

Integration is not a "one-size-fits-all" process. Depending on the product's requirements, eFabric™ hardware supports multiple communication modes:

• SPI (Serial Peripheral Interface): Used for high-speed firmware loading and when the host needs to extract raw feature data from the NDP for further analysis.

• UART (Universal Asynchronous Receiver-Transmitter): Preferred for simple, low-bandwidth command exchanges and status updates, minimizing the number of traces required on the PCB.

Duty Cycle (D)

To calculate the total system power savings, engineers use the Duty Cycle of the host processor. If the host is awake for ton during a total period T:

$$D = \frac{t_{on}}{T}$$

By using the NDP, ton is reduced to only those moments where a relevant event occurs, typically dropping D by over 95%.

Total System Power $(P_{sys})$

$(P_{sys})$ represents the Total Average System Power Consumption, calculated as the weighted sum of the power consumed during the host's active state and its deep-sleep state based on the operational duty cycle.

$$P_{sys} = (D \times P_{active}) + ((1 - D) \times P_{sleep})$$

💡Hardware Decoupling

"Always treat the NDP as a separate power domain. This allows you to completely shut down the power to the rest of your system while the NDP continues to run on a dedicated low-leakage LDO (Low Dropout Regulator)."

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The System-on-Module (SOM) Approach: TML120

While the NDP silicon is the engine, the TML120 is the vehicle that makes deployment practical. Designing a high-speed neural processing board from scratch—a "chip-down" design—involves complex signal integrity challenges and lengthy certification cycles. The TML120 eliminates this friction by providing a pre-validated, production-ready System-on-Module (SOM).

A. Why Use a Module? (Speed to Market)

Adopting a SOM approach allows developers to focus on their application logic rather than the minutiae of high-speed PCB layout.

• Integrated Signal Integrity: The TML120 handles the critical, high-speed routing between the NDP and its dedicated Flash memory internally. This prevents timing errors and electrical noise that often plague custom designs.

• Reduced Design Risk: Because the power sequencing and clocking are "baked into" the module, the risk of hardware failure during the prototyping phase is virtually eliminated.

• Simplified Bill of Materials (BOM): Instead of sourcing multiple components (NDP, Flash, Oscillators, LDOs), the engineer simply sources one part: the TML120.

B. On-Board Resource Synergy

The TML120 is more than just a carrier; it is a balanced ecosystem where every component is tuned for the NDP:

• Memory Matching: The on-board Flash is specifically selected for its low-power read characteristics, ensuring that "Weight Loading" (bringing the neural network into the gates) doesn't spike the power budget.

• Physical Density: Measuring only a few millimeters, the TML120 provides an incredible amount of "Intelligence per Square Millimeter," making it ideal for space-constrained devices like hearables, rings, or compact industrial probes.

C. The Path to Mass Production

For many eFabric™ users, the TML120 is the permanent solution. It is fully certified (FCC/CE/RoHS), meaning your end-product can bypass many of the expensive and time-consuming radio and emissions tests required for discrete chip designs.

💡The Scaling Strategy

"Use the TML120 for your MVP (Minimum Viable Product). It allows you to prove your 'Always-On' features and power benchmarks in weeks. While a chip-down design might save a few cents at a million-unit scale, the TML120 saves months of engineering time and thousands in certification costs for everything up to that point."

Module Efficiency: We can define the Integration Efficiency ($\eta_{int}$) as a function of saved PCB area ($A_{saved}$) and reduced component count ($C_{red}$).

$$\eta_{int} = \frac{A_{saved} + C_{red}}{\text{Design\_Time}}$$

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Host-Controller Interaction: UART and SPI Protocols

Once the TML120 has identified a pattern, it must communicate that discovery to the rest of the system. The module acts as an autonomous "intelligent peripheral," interacting with the primary Host Controller (the Application Processor) through standard serial protocols. The choice between SPI and UART depends on the required data throughput and the complexity of the interaction.

A. SPI (Serial Peripheral Interface): The High-Speed Link

SPI is the primary interface used during the initialization and heavy data-exchange phases of the eFabric™ lifecycle.

• Firmware & Model Loading: Because neural network models can be several hundred kilobytes, SPI’s high clock speeds (often up to 20MHz) are essential for "booting" the NDP quickly.

• Feature Extraction: In some advanced use cases, the host may want to "peek" into what the NDP is seeing. SPI allows the host to pull raw spectral features or Mel-spectrogram data for secondary analysis without bottlenecking the system.

• Master/Slave Dynamic: Typically, the Host Controller acts as the SPI Master, while the TML120 acts as the Slave, responding only when addressed.

B. UART (Universal Asynchronous Receiver-Transmitter): The Command Link UART is often used for simpler, low-bandwidth communication or for debugging purposes.

• Result Reporting: If the application only needs to know which keyword was detected (e.g., "ID 1" for "Hey Siri"), a simple UART string or byte is the most pin-efficient method.

• Simplified Routing: UART requires only two wires (TX/RX), making it ideal for space-constrained PCBs where routing a 4-wire SPI bus is physically difficult.

• Asynchronous Alerts: Unlike SPI, which requires the Master to "poll" the Slave, UART can be configured to send a burst of data as soon as an event occurs, provided the Host's RX buffer is active.

C. Protocol Selection Matrix

Choosing the right "language" for your hardware depends on your specific application needs:

Feature	SPI (Recommended)	UART
Data Rate	High (Multi-Mbps)	Low (Typically 115.2 kbps)
Primary Use	Loading Models / Feature Streaming	Command & Control / Debugging
Pin Count	4 Wires (+ Interrupt)	2 Wires (+ Interrupt)
Complexity	Moderate	Low

The "Handshake" Mechanism: Regardless of the protocol, the most critical pin in the integration is the IRQ (Interrupt Request). The TML120 uses this pin to signal the Host: "I have something to tell you." This prevents the Host from having to waste energy constantly "polling" the SPI or UART bus.

Transfer Time ($t_{transfer}$):
To calculate the time required to load a model of size $S_{model}$ at a clock frequency $f_{clk}$:

$$t_{transfer} = \frac{S_{model}}{f_{clk} \times \text{bus\_width}}$$

Baud Rate Calculation (UART): The speed at which data is transmitted over the UART interface:

Baud Rate $\frac{f_{osc}}{16 \times (UBRR + 1)}$.

• $f_{osc}$ The Oscillator Frequency. of the system clock, measured in Hertz, e.g., 16MHz.
• UBRR (UART Baud Rate Register): This is the integer value you actually program into the hardware register.

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Power Profiles and Triggering Mechanisms

The ultimate goal of the eFabric™ hardware architecture is to maximize the Battery Life of the end device. Achieving this requires a sophisticated power management strategy where the TML120 transitions through various "Power Profiles" based on the environment. By utilizing an autonomous triggering mechanism, the system ensures that high-power components are only active when absolutely necessary.

A. The Hierarchy of Power States The TML120 operates in three primary modes, each defined by which internal blocks (DSP, Neural Engine, Management Core) are active: Deep Sleep (Standby): The neural engine is powered down, and only the management core is alive to listen for a wake-up signal. Current draw is in the single-digit microamp range.

1. Always-On Monitoring (Inference Mode): The DSP is active, streaming data into the Neural Engine. The chip is "thinking" in real-time but remains in a specialized low-power state. Current draw is typically 150A.

2. Active Communication (Host Alert): Once a detection occurs, the high-speed interfaces (SPI/UART) are enabled to alert the host. This is the highest power state but lasts for only a few milliseconds.

B. The Triggering Logic: "Confidence over Threshold" Triggering is not a binary process; it is a probabilistic one. To prevent "False Alarms" from wasting battery life, eFabric™ uses a Multi-Stage Triggering mechanism:

• Step 1: The Neural Score: As the NDP processes data, it generates a "Confidence Score" for each frame.

• Step 2: The Threshold Filter: You define a specific threshold (e.g., 0.85 confidence). If the score stays below this, the NDP remains silent.

• Step 3: The Match Window: To avoid triggers from random noise spikes, the system can be configured to require multiple high-confidence frames within a specific window (e.g., 3 out of 5 frames) before firing the interrupt.

C. Total System Power Analysis

When calculating the success of an eFabric™ integration, engineers look at the System Power Reduction Ratio ($R_{pwr}$). This compares a traditional "Always-On CPU" design to the "NDP-Gatekeeper" design:

$$R_{pwr} = \frac{P_{CPU\_Always}}{P_{NDP\_Always} + (D \times P_{CPU\_Active})}$$

• D (Duty Cycle): The small percentage of time the main CPU is actually awake.
• The Result: In most applications, Rpwr exceeds 100x, meaning the battery will last 100 times longer using the TML120 triggering logic.

📊Data Insight: The "Quiet Room" Effect

"In environments with low background noise, the NDP can drop into an even lower power state called Adaptive Power Scaling, where it reduces its internal clock frequency until the ambient noise levels increase, further squeezing every milliwatt out of the battery."

💡False Trigger Mitigation

"If your device is triggering too often due to environmental noise (like a fan), don't just raise the threshold. Use Background Noise Injection during training (Section 4.2.3) to teach the NDP to ignore that specific power profile."